This invention relates to a semiconductor test system for testing semiconductor devices with high speed, and more particularly, to a semiconductor test system which can operate in a pin multiplex mode to generate test signals higher than two times of more than a repetition rate of a reference clock signal without involving limitations existed in the conventional technology.
The semiconductor test system of the present invention is directed to a test system having a function of a pin-multiplex mode. In a pin-multiplex mode, test signals of a plurality of tester channel (test pin) are multiplexed in a time sequential manner so that the test signal of high repetition rate can be generated for testing a semiconductor device. Thus, a pin-multiples mode in the semiconductor test system functions in a manner similar to a parallel-serial conversion process.
Such a pin-multiplex mode is typically performed in a per-pin structured test system. Such a semiconductor test system is also called a per-pin IC tester. Here, a per-pin IC tester refers to a semiconductor test system wherein all of the hardware resource for generating test parameters such as signals are independently provided for each test channel (tester pin) of an IC tester. Consequently, in a per-pin IC tester, various test parameters for a semiconductor devices under test (DUT) can be set independently for each pin of the DUT. Although the present invention is advantageously applicable to the per-pin IC tester, it is also feasible to other types of semiconductor test system such as a shared resource type IC tester.
In testing semiconductor devices such as ICs and LSIs by a semiconductor test system, such as an IC tester, a semiconductor IC device to be tested is provided with test signals produced by an IC tester at its appropriate tester pins (channels) at predetermined test timings. The IC tester receives output signals from the IC device under test generated in response to the test signals. The output signals are strobed by strobe signals with predetermined timings to be compared with expected data to determine whether the IC device properly performs the intended functions.
Typically, timings of the test signals and strobe signals are defined relative to a tester rate or a tester cycle of the IC tester. Generally, the various timings of the tester cycles, test signals and strobe signals are generated based on a reference clock. The reference clock is produced by a high stability oscillator, for example, a crystal oscillator provided in the IC tester. When the required timing resolution in an IC tester is equal to or an integer multiple of the highest clock rate (one clock cycle) of the reference clock oscillator, variety of timing signals can be generated by simply dividing the reference clock by a counter or a divider.
However, IC testers are usually required to have timing resolution higher than the highest clock rate, i.e., the shortest time period, of the reference (system) clock. For example, in the case where a reference clock cycle used in an IC tester is 10 ns (nanosecond), but the IC tester needs to have timing resolution of 0.3 ns or higher, it is not possible to achieve such timing resolution by simply applying or dividing the reference clock.
To generate such timing signals, it is known in the prior art that such timings are described by timing data in a test program. For describing the timings with the resolution higher than the reference clock rate, the timing data is described by a combination of an integer multiple of the reference clock time interval (integral part) and a fraction of the reference clock cycle (fractional part). Such timing data is stored in a timing memory and read out at each cycle of the test cycle. Thus, in each test cycle, test signals and strobe signals are generated with reference to the test cycle, such as a start point of each cycle, based on the timing data.
FIG. 4 is a schematic block diagram showing an example of a conventional semiconductor test system. The example of FIG. 4 shows a basic configuration of a semiconductor test system having a shared resource structure. A pattern generator 2 generates a test pattern to be provided to a DUT (device under test) 9 and an expected value pattern to be provided to a pattern comparator 7. A timing generator 3 generates a timing pulse signal to synchronize the timing of the whole system, and provides the timing pulse signal to the pattern generator 2, the pattern comparator 7, a wave formatter 4, an analog comparator 6.
The timing generator 3 provides the timing pulse (tester rate pulse) and timing data to the wave formatter 4. Based on the pattern data from the pattern generator 2 and the timing pulse and timing data from the timing generator 3, the wave formatter 4 forms a test signal having a specified waveform and timings and provides the test signal to a driver 5. The pattern data is also called format control data (FCDATA) which defines rising and falling edges of the test signal waveform. The timing data (timing set data) defines timings (delay times) of the rising and falling edges of the waveform relative to the test cycle. Although not shown in FIG. 4, the wave formatter 4 includes a set/reset flip-flop to form the test signal to be provided to the driver 5. The driver 5 regulates the amplitude of the test signal to a predetermined level and applies the test signal to the DUT 9.
A response signal from the DUT 9 is compared with a reference voltage at a predetermined strobe timing by the analog comparator 6. The resultant logic signal is provided to the pattern comparator 7 wherein a logic comparison is performed between the resultant logic pattern from the analog comparator 6 and the expected-value pattern from the pattern generator 2. The pattern comparator 7 checks whether two patterns match with each other or not, thereby determining pass or failure of the DUT 9. When a failure is detected, such fail information is provided to a fail memory 8 and is stored along with the information of the failure address of the DUT 9 from the pattern generator 2 in order to perform failure analysis later.
To generate each signal to perform the foregoing operations, a memory is provided with a data table that stores data in each of the pattern generator 2, the timing generator 3, and the wave formatter 4. The data in the data table is formed by a test program that a user or programmer has produced based on the specifications of the DUT 9. The test program is provided to each unit in the IC tester from a test processor 1 through a tester bus in FIG. 4. Thus, the test processor 1 controls an overall operation of the test system based on the test program. In the table of the pattern generator 2, test pattern data for a plurality of channels is provided, thereby allocating the pattern data to each of the terminal pins 1-n of the DUT 9.
The memory in the timing generator 3 includes a rate set table and a clock set table. The rate set table stores the rate data indicating the tester rate or test cycle (may also be referred to as xe2x80x9cRATExe2x80x9d). The clock set table stores timing data showing the timings (delay times) of edges in a test signal waveform to be produced by the wave formatter 4. For example, the delay times are defined with reference to the start point of the test cycle. Such rate data and timing data are provided from the pattern generator 2 to the timing generator 3 prior to the start of the test operation. In contrast, pattern data showing the edges in the test signal waveform is provided in real time to the timing generator 3.
Thus, the timing generator receives the timing data (timing set data) in advance while it receives the pattern data (format control data FCDATA or edge data) during the operation. Based on the timing data and pattern data, the timing pulse (tester rate pulse) and the timing data are generated by the timing generator 3 which are provided to the wave formatter 4 to form the test signals. In general, various combinations of the above data are used to generate test signals of complex waveforms.
As noted above, a modern semiconductor test system needs to generate test signals with the timing resolution higher than a reference clock cycle. Thus, the delay data generated by the timing generator 3 is described by a combination of an integer multiple of the reference clock cycle (integral part) and a fraction of the reference clock cycle (fractional part). For example, the fractional part data shows delay time resolution of xc2xd, xc2xc, xe2x85x9, {fraction (1/16)} of the reference clock cycle. Within the context of the present invention, the timing data may also be referred to as HR (high resolution) data or a HR signal. Typically, the delay time indicated by the integral part of the timing data HR is produced by counting the integral part data. The delay time indicated by the fractional part of the timing data HR is produced by an analog type variable delay circuit.
In the data table of the wave formatter 4, data relating to waveform modes are provided. Such waveforms include a return-to-zero (RZ) waveform, a non-return-to-zero (NRZ) waveform and an exclusive OR (EOR) waveform. The test signal is created by combining the pattern data (format control data or edge data) from the pattern generator 2 and timing (rate) pulses and timing data (delay time data) from the timing generator 3, and the waveform data in the wave formatter 4. The test signal is provided to the driver 5 whereby incorporating a predetermined amplitude.
Because of the advancement in the semiconductor IC technology, IC devices to be tested are becoming more and more complicated and high speed as well as high density. To test such IC devices, an IC tester has to be able to generate complicated test patterns at high speed. The IC tester having the shared resource structure such as shown in FIG. 4 is considered economical but not enough to test recent IC devices with high complexity and high speed. Here, the shared resource IC tester refers to a tester in which tester resources such as a timing generator and reference voltages are commonly used for all tester channels (test pins).
In contrast, an IC tester of a per-pin structure is considered more appropriate to test such complicated and high speed IC devices. The per-pin tester refers to a tester which is capable of independently set test parameters to be applied to the DUT 9 for each pin. In other words, a per-pin structured IC tester has tester resources such as a timing generator for each tester pin (channel) separately from the other tester pins.
Compared to the shared resource tester that shares the test parameters for each terminal pin of the DUT 9, the per-pin tester is better suited for testing high speed LSIs since a complex test pattern and timing can be generated more freely since it can produce the test parameters for each terminal pin of the DUT 9 independently from the other pins. In a typical per-pin IC tester, the timing generator 3 and wave formatter 4 in FIG. 4 are allocated to each tester pin, i.e., to each terminal pin of the DUT 9.
FIG. 5 is a block diagram showing an example of a conventional per-pin IC tester. The example of FIG. 5 is directed to the structure of one tester pin for generating a test signal for a terminal pin of a DUT. The per-pin tester includes a waveform memory (WFM) 11, a timing generator 3, a real time selector 12, and a wave formatter 4. The wave formatter 4 supplies a test signal to a driver such as shown in FIG. 5 to determine the amplitude thereof before being provided to a device under test (DUT).
The waveform memory (WFM) 11 receives test pattern data from the pattern generator 2, and transmits pattern data and timing data to a timing generator 3. The pattern data is also called format control data (FCDATA) or edge data which defines rising and falling edges of the test signal waveform. The timing data (timing set data) defines timings (delay times) of the rising and falling edges of the waveform relative to the test cycle. The timing generator 3 receives the timing data (timing set data) in advance while it receives the pattern data (format control data FCDATA or edge data) during the operation.
In this example, two groups (T1 and T2) of edge data showing set and reset timings are provided to the timing generator 3. Namely, a set timing T1S, a reset timing T1R, a set timing T2S and a reset timing T2R as shown in FIG. 5. These set and reset timings are ultimately used in the wave formatter 4 to produce a test signal by driving a set/reset flip-flop therein with the defined timings. In other words, the set and reset timings determine timings of rising and falling edges of the test signal waveform within a tester rate (test cycle). It should be noted that, in the standard operation of the IC tester, one of T1S or T1R and one of T2S or T2R can be validly used in one test cycle.
Based on the timing data and edge data (format control data) from the waveform memory 11, the timing generator 3 produces a timing pulse (also referred to as a gate signal GATE) and high resolution (HR) timing data. Typically, the timing pulse (gate signal) defines a start point of the tester rate (test cycle) and the timing data HR defines a delay time of the set or reset signal relative to the timing pulse. The timing generator 3 allocates the timing pulses and the timing data HR to a set signal path and a reset signal path of the wave formatter 4 via the real time selector 12.
More particularly, the timing generator 3 produces, in synchronism with the reference clock (not shown), the gate signal (timing pulse) GATE, the high resolution timing data HR, and the group select signal (not shown). Based on the group select signal, either one of the groups T1 or T2 of the timing generator is selected. As noted above, the gate signal GATE defines a reference timing (for example, a start of each test cycle) for rising and falling edges of the test signal. The timing data HR shows a delay time of the edges of the test signal waveform with reference to the gate signal GATE. The delay time defined by the timing data HR includes an integer multiple of the reference clock cycle and a fraction of the reference clock cycle.
The real time selector 12 selects and provides the gate signal GATE and the timing data HR to a set signal path or a reset signal path in the wave formatter 4. An example of the allocation of the timing pulse and the timing data HR through the real time selector 12 is shown in a truth table of FIG. 8, which is directed to the set signal path. Although not shown, the same allocation is also applicable to the reset signal path. This table shows that the logical combinations of GATE-T1 and GATE-T2 in the left part of the table determine the timing pulse (GATE-SET) and the timing data (HR-SET) in the right part of the table to be provided to the set signal path in the wave formatter 4.
As shown in the table of FIG. 8, when the gate signal (GATE-T1) of the group T1 is xe2x80x9c0xe2x80x9d and the gate signal (GATE-T2) of the group T2 group is xe2x80x9c0xe2x80x9d, the timing pulse (GATE-SET) and the timing data HR are xe2x80x9c0xe2x80x9d. Here, xe2x80x9c0xe2x80x9d indicates non-existence while xe2x80x9c1xe2x80x9d, indicates existence. When the GATE-T1 is xe2x80x9c0xe2x80x9d and the GATE-T2 is xe2x80x9c1xe2x80x9d, the timing pulse (GATE-SET) and the timing data HR of the group T2 are provided to the wave formatter 4. When the GATE-T1 is xe2x80x9c1xe2x80x9d and the GATE-T2 is xe2x80x9c0xe2x80x9d, the timing pulse (GATE-SET) and the timing data HR of the group T1 are provided to the wave formatter 4. If the GATE-T1 and GATE-T2 are xe2x80x9c1xe2x80x9d, timing pulse (GATE-SET) and smaller one of the timing data HR-T1 or HR-T2 are provided to the wave formatter 4.
The wave formatter 4 generates a set signal in the set signal path and a reset signal in the reset signal path. In FIG. 5, the set signal path is the upper half of the wave formatter 4 and the reset signal path is the lower half of the wave formatter 4. The set signal and reset signal are provided to a set/reset flip-flop 13. Each of the set and reset signal paths includes a coarse delay circuit 14 and a fine delay circuit 18, a register 17, an accumulator 17, and an AND gate 15. The coarse delay circuit 14 produces a delay time defined by the integral part of the timing data HR. The fine delay circuit 18 adds a delay time defined by the fractional part of the timing data HR to the output signal of the coarse delay circuit 14. If necessary, the register 16 provides a delay time to the accumulator 17 for adjusting skews (timing difference) between test channels.
The coarse delay circuit 14 is formed, for example, of a down counter for counting the number of the reference clock pulse defined by the integral part of the timing data. The integral part of the timing data is received through the higher bits of the output of the accumulator 17. Thus, the coarse delay circuit 14 produces a set signal which is delayed by the integer multiple of the reference clock cycle defined by the timing data HR. The AND gate 15 is provided for retiming the set signal from the delay circuit 14.
Based on the fractional part delay data received through the higher bits of the timing data HR, the fine delay circuit 18 provides a delay time smaller than one cycle of the reference clock to the set signal from the coarse delay circuit 14. The fine delay circuit 18 is an analog delay circuit formed, for example, of series connected CMOS gates. Thus, the set signal having a delay time defined by the timing data HR is supplied to the set/reset flip-flop 13 to produce a rising edge of the test signal. In the same manner, the reset signal having a delay time defined by the timing data HR is supplied to the set/reset flip-flop 13 to produce a falling edge of the test signal.
In the foregoing, it should be noted that an IC tester cannot produce a signal having a time interval smaller than one cycle of a reference clock. One of the reasons is that each and every operation in the IC tester is synchronized with the reference clock so that a signal having a repetition rate smaller than the reference clock is not discernible by the system. The reference clock is the smallest time unit in terms of the synchronized operation in the test system. Therefore, if the time interval of two set signals smaller than the reference clock cycle is provided to the same set signal path, such set signals cannot properly produce an intended edges in the test signal. This is true for the reset signals in the reset signal path as well.
FIG. 6 is a timing chart showing the operation of the IC tester of FIG. 5. In this example, the tester rate (test cycle) RATE of FIG. 6(A) has a time length of four cycles of the reference clock REFCLK of FIG. 6(B). The pattern of FIG. 6(C) is a test pattern specified by the user. The user specified test pattern shows the set edge data T1S handled by the group T1 timing generator and the reset edge data T2R handled by the group T2 timing generator in the first test cycle. In the second test cycle, the test pattern shows the set edge data T2S handled by the group T2 timing generator and the reset edge data T1R handled by the group T1 timing generator. The allocation of the timing edges (edge data) and the groups of timing generators are freely specified by the user of the IC tester so long as one edge by one group of timing generator is specified in one test cycle.
The GATE SET of FIG. 6(D) in this case is an output signal of the coarse delay circuit 14 in the set signal path of the wave formatter 4 which is delayed by an integer multiple of the reference clock cycle. The fractional part of the timing data HR shown in FIG. 6(E) defines a fine delay time smaller than one cycle of the reference clock. The fine delay time is added to the GATE SET of FIG. 6(D) by the fined delay circuit 18 so that the set signal of FIG. 6(F) is produced.
Similarly, the GATE RES of FIG. 6(G) in this case is an output signal of the coarse delay circuit in the reset signal path of the wave formatter of FIG. 5 which is delayed by an integer multiple of the reference clock cycle. The fractional part of the timing data HR shown in FIG. 6(H) defines a fine delay time smaller than one cycle of the reference clock. The fine delay time is added to the GATE RES of FIG. 6(G) by the fined delay circuit so that the reset signal of FIG. 6(I) is produced.
By the set signal and reset signal formed in the foregoing, the flip-flop 13 produces an output (test) signal of FIG. 6(J) having the edge timings specified by the user. The set and reset signals in the second test cycle are produced in the manner similar to the above. In this example, since the pulse interval in the set signal path or reset signal path is greater than the reference clock cycle, the intended timing edges in the test signal can be produced at the output of the flip-flop 13.
In the conventional semiconductor test system shown in FIGS. 4-6, there arises a problem for generating a test signal having desired edge timings when the system is in a high speed operation such as a pin multiplex mode. For example, when the time interval between two edges in the same path (set signal path or reset signal path) is smaller than one cycle of the reference clock, the system cannot properly produce such edges because of the reason noted above.
To fully evaluate the high speed IC devices, a per-pin structured IC tester is designed to operate in a pin-multiplex mode for achieving a high speed test pattern generation. In such a pin-multiplex mode, test signal edges for a plurality of tester channels (device pins) are combined so that the repetition rate (number of edges) of the test signal is increased in proportion to the number of tester channels multiplexed.
FIG. 7 shows a timing relationship in the pin multiplex mode operation in the conventional IC tester. In this example, it is assumed that the test cycle (tester rate RATE) is set to the highest rate in which the test cycle is almost the same as the reference clock cycle. Thus, as shown in. FIGS. 7(A) and 7(B), the test cycle RATE and the reference clock REFCLK show substantially the same time length. The intended output signal OUT is shown in FIG. 7(C) where timing edges for two test channels (odd O and even E channels) are multiplexed.
In this example, in the first half of the first test cycle designated by aF and aL, the timing edges T1O and T3O of the odd tester channel (pin) are used. In the second half of the first test cycle designated by bF and bL, the timing edges T1E and T3E of the even tester channel (pin) are used. Further, in the second test cycle, FIG. 7(C) shows the first timing edge T1O. The timing edges T1O and T30 are respectively allocated to the former half aF and latter half aL of the first half test cycle. The timing edges T1E and T3E are respectively allocated to the former half bF and latter half bL of the second half test cycle. References T1 and T3 indicate two timing generator groups such as shown in FIG. 5 by T1 and T2.
In this example, as shown in FIG. 7(C), there arises a situation where the time interval K of the two rising edges (set signals) T3O and T1O is smaller than one cycle period of the reference clock. Since signals in the same signal path (set signal path in this case) having the time interval smaller than the reference clock cycle is not discernible as described in the foregoing, the IC tester cannot generate the intended test signal of FIG. 7(C). Therefore, there is a need for a semiconductor test system to overcome this problem so that any timing settings by the user can produce a test signal of intended timing edges.
It is, therefore, an object of the present invention to provide a semiconductor test system which is capable of generating a test signal having a time interval between the timing edges of the same direction which is smaller than one cycle of the reference clock.
It is another object of the present invention to provide a semiconductor test system which is capable of generating a high speed test signal by multiplexing timing edges of a plurality of tester channels.
It is a further object of the present invention to provide a semiconductor test system which is capable of detecting inappropriate settings in the edge data by the users and allocating the edge data so that an intended edge is produced in a different signal path in the test system.
It is a further object of the present invention to provide a semiconductor test system which is capable of generating an intended test pattern in a pin multiplex mode even when the edge data set by the user is inappropriate.
In the present invention, edge data is detected whether the current edge data is the same as the previous edge data, and if so, the current pattern edge is removed from the user specified time position and shifted to the time position where there is an actual change of edge in the test signal waveform. As a result, the situation where the time interval smaller than the reference clock in the same signal path can be obviated.
The semiconductor test system of the present invention for testing a semiconductor device includes a waveform memory for storing edge data which defines edges of a test signal waveform to be supplied to a semiconductor device under test based on a test program, a timing generator for generating timing data and a timing pulse for each test cycle, a wave formatter for generating a set signal and a reset signal for producing the test signal waveform in response to the timing data and the timing pulse from the timing generator, and a virtual timing generator provided between the waveform memory and the timing generator for detecting a relationship between previous edge data and current edge data from the waveform memory corresponding to each of the set signal and the reset signal and removing the current edge data when the current edge data is the same as the previous edge data and allocating the current edge data to a time position where there is an actual change of edge in the test signal waveform.